- 合成期
- synthesis: n. (pl. -ses ) 综合，【化学】合成；【逻辑 ...
- stage: n. 1.讲台；舞台；戏院，剧场；〔the stage〕 ...
- for synthesis: 合成用
- synthesis: n. (pl. -ses ) 综合，【化学】合成；【逻辑学】综合(法)；【语言学】综合(性)；语词的合成；【医学】接合；【物理学】合成综合。
- a stage: a阶树脂
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synthesis stage中文什么意思
- 合成期
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例句与用法
- At the logic synthesis stage , we make some research on the principles of logic synthesis at first , then by utilizing tsmc0 . 25um process , choosing the worst case that the workable temperature can be high to 125 degrees centigrade and the supply voltage is as low as 2 . 25v , and introducing the wireload library for effectively simulating delay and power consumption of wire connection , and taking the same clocks as in simulation , the critical path is 15 . 3ns and the chip area is 0 . 395mm2
在进行逻辑综合时首先对逻辑综合的原理作了一定的了解，然后利用tsmc的0 . 25 m的工艺库，工作电压为2 . 25v ，工作温度最高可达到125摄氏度的最坏情况下，进行逻辑综合时引入了wireload库以便有效的模拟连线所引起的延迟及功耗，采用与模拟时相同的时钟，关键路径为15 . 3ns ，芯片面积为0 . 395mm ~ 2 。